Leading G.fast DPU Chipset - Sckipio
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DP3000 G.FAST DPU CHIPSET

Everything You Need to Succeed

OVERVIEW

The Sckipio DP3000 G.fast DPU Chipset includes the DP3000-D Digital Front-End (DFE) System-On-Chip (SOC) solution and the DP3000-A Analog Front-End chip. Both are used together to implement a Distribution Point Unit (DPU), typically for a Fiber-to-the-Distribution-Point (FTTdp) installation.

 

The DP3000-D implements four FTU-O transceivers that comply with the ITU G.fast recommendations (G.9700/1) as well as additional functionalities required within the Distribution Point Unit (DPU) and defined within the G.9701 System Reference Model Recommendation.

DP3000 G.fast DPU Chipset

DP3000 G.fast DPU Chipset

The Sckipio DP3000 is designed for use in building distribution point units to deploy ultra high speed broadband for MDU, Single Family Units and businesses. It also is an excellent solution for cellular backhaul.

REFERENCE MATERIAL

Broad Standards Support
  • Fully compliant with the ITU-T G.fast Recommendation (G.9700/1)
  • Supports the complete 106a profile
  • Compliant with ITU-T G.999.1 interface recommendation
  • Supports ITU-T G.997.1 and future extensions for G.fast
  • Support for TR-156 and TR-167 Broadband Forum Architectures
  • Support for IEEE 1588 Time Synchronization
  • Supports ITU G.994.1 G.hs
  • Spectrally co-existent with legacy technologies, e.g. ADSL, VDSL
Full G.fast Performance
  • Bandwidth: 2 – 106MHz (programmable)
  • Max PHY rate: 1Gbps per line
  • Flexible downlink/uplink bit rate ratio
Highly Efficient Design
  • 4-port Digital Front End
  • All “on-chip” memory
  • Ethernet Relay support
  • Four Analog Front-End (DP3000-A) chips, each with an integrated Line Driver
Vectoring Control Engine
  • On-chip VCE providing system-level vectoring
  • Vectoring group size of up to 64 lines
  • Scalable VCE processing power
Low Power Consumption
  • Support for forward or reverse power
  • Average end-to-end transceiver power of 1.5 watts per line
  • Low power modes supported across the whole reference design (DFE and AFE)
  • Multiple power save modes lowering actual consumption under real life conditions
  • Full discontinuous mode support for lower actual consumption under real-life conditions
  • Support for L2.0, L2.1 low power states
Interfaces
  • 1G, 2.5G and 10G interfaces with G.999.1 support
  • RGMII, GMII, SGMII, 2.5G SGMII and XAUI interfaces supported
  • Ethernet Backplane support using 1000BASE-KX and 10GBASE-KX4
  • Support for 1000BASE-X and SGMII (XGXS PHY)
  • MDIO management master and slave with Clause 22 and Clause 45 support
  • Ethernet MAC and PHY mode support
L2+ Networking
  • 1:4 Ethernet to G.fast port switching per chip.
  • Ethernet Relay Port for G.fast port scaling
  • Classification based switching on VLAN, Ethernet MAC Address (DA/SA) or G.999.1 Stream ID.
  • Up to 8 QoS priority queues per G.fast transceiver port
  • QoS-aware congestion control when G.999.1
  • “Learning Bridge” mode for DA to G.fast port mapping
  • Multicast packet replication based on multicast groups
PHY-related
  • Very low noise receive path
  • Robust with high immunity to disturbers
  • Fast Online Reconfiguration (OLR)
  • Short train/retrain time
  • Flexible DTU size
Time and Synchronization
  • Time-of-Day (ToD) synchronization to external clock reference
  • Synchronization using low accuracy management protocol, IEEE 1588 or one PPS signal
  • 8KHz Network Time Reference (NTR) support between DP and CPE
Management and Configuration
  • Configuration interface for customized functionality
  • Upgradeable firmware
  • Full statistics and performance monitoring
Miscellaneous
  • Industrial temperature ranges (-40°C to 85°C) to support outdoor applications
  • Full development system and reference design for fast time-to-market